The present invention relates to semiconductor devices and, more particularly, to erasing methods for nonvolatile memory cells.
Nonvolatile memory devices, unlike volatile memory devices, typically maintain data even when power is not supplied. Accordingly, nonvolatile memory devices, such as flash memory devices, are widely used in, for example, file storage systems, memory cards, portable devices, and other applications.
A nonvolatile memory cell may be programmed by a well-known hot electron injection method. Techniques for erasing a programmed nonvolatile memory cell may vary. For example, an F-N tunneling mechanism or a hot-hole injection mechanism may be used.
A nonvolatile memory cell having a silicon-oxide-nitride-oxide-silicon (SONOS) gate structure may be programmed by inducing hot electron injection like a memory cell having a stacked gate structure. In other words, a high voltage may be applied to a gate electrode to cause an electrical potential difference between a source and a drain. As a result, hot electrons nay be formed in a channel region near the drain (or source), and move over an energy barrier of a tunnel oxide layer to be injected into a charge storage layer, such as a trap dielectric layer. When the electrons are injected into the charge storage layer, a threshold voltage of the device typically increases. Accordingly, when a lower voltage than the increased threshold voltage is applied to the gate electrode, current does not flow in the programmed cell, which may be utilized to read stored data. Electrons within the trap dielectric layer may be erased using a F-N tunneling mechanism, a hot hole injection mechanism, or other technique.
In detail, the charge storage layer, such as the trap dielectric layer, may be a nonconducting layer, so that the electrons injected during the programming operation generally do not freely move in the trap dielectric layer. Accordingly, in order to eliminate the injected electrons, hot holes may be injected in a region equal to a region of the trap dielectric layer where the injected electrons are distributed, or F-N tunneling may occur in the region.
For example, a method of erasing a nonvolatile memory cell using F-N tunneling may erase electrons within the charge storage layer using an electrical potential difference between the gate electrode and the source region to lower the threshold voltage of the cell. In contrast, a method of erasing a nonvolatile memory cell using a hot hole injection technique may involve injecting the hot holes generated between the source region and the substrate into the charge storage layer. However, the erasing speed using F-N tunneling may be very slow, so that the hot hole injection erasing technique has recently gained favor.
A conventional erasing technique for a nonvolatile memory cell is described in Japanese Laid-Open Patent Publication No 1992-105368 entitled “Nonvolatile Semiconductor Storage device” to AJIKA NATSUO et al. According to AJIKA NATSUO et al, a control gate voltage Vg is set at −12V while a drain voltage Vd is maintained in a floating state during the erasing step. Later, 5V is applied as a source voltage Vs. Such a technique may cause a problem for hot hole injection erasing using hot holes generated by band-to-and tunneling (BTBT). Specifically, when a hot hole injection erasing method is employed in the SONOS-type nonvolatile memory, the voltage applying method according to AJIKA NATSUO et al may cause several problems.
When a source voltage Vs is applied after a gate voltage Vg is applied, the BTBT current may be high due to the hot holes generated by a strong vertical electric field generated by the gate voltage and the source voltage. Even when the gate voltage Vg and the source voltage Vs are simultaneously applied, the BTBT current may be high due to the hot holes generated by a strong vertical electric field generated by the gate voltage and the source voltage. Accordingly, the tunnel oxide layer of the SONOS-type nonvolatile memory cell may be damaged by the high BTBT current. Such damage to the tunnel oxide layer of the SONOS-type nonvolatile memory cell may degrade endurance and retention characteristics of the nonvolatile memory cell. As a result, reliability of the nonvolatile memory device may be degraded.